In semiconductor processing technology, planar substrate surfaces which are horizontal with respect to a wafer surface are patterned by photolithographic methods in combination with selective etching processes. During the processing of integrated circuits, reliefs with a pronounced topography are formed on the wafer or substrate surface. Typically, this type of relief includes surfaces which are inclined or vertical with respect to the substrate surface. As sizes of integrated circuits continue to shrink, it is becoming more and more necessary to pattern vertical or inclined device surfaces so as to functionally differentiate these devices over their vertical extent while still maintaining pattern alignment. Examples of these types of semiconductor devices include deep trench capacitors, stacked capacitors, and vertical transistors.
Currently, it is not possible to put patterns directly on walls which are vertical with respect to the substrate surface using conventional photolithographic techniques. Usually, vertical wall patterning of this nature is accomplished using a suitable filler material which, when partially filling in a trench, acts as a mask for the portions of the wall located underneath while allowing for processing of the walls above the filler material. For example, when an oxide is to be deposited exclusively on vertical walls below a filler material, the oxide is first deposited or produced over the entire surface of the relief. The relief or trench is initially completely filled with a suitable filler material. Then, the filler material is recessed back to a depth that just covers the desired oxide. After uncovered sections of the oxide are removed, the remaining filler material is removed.
Alternatively, when an oxide is to be deposited or produced only in upper regions of a vertical wall, an etching stop layer, for example, a nitride layer is first provided over the entire surface of the entire relief pattern. A different material, susceptible to directional etching, for example, polycrystalline silicon, is used to fill the relief, and is etched back as far as the desired coverage depth of the final vertical oxide. After the etching stop layer is removed from the unfilled sections of the walls, an oxide is deposited or generated using a thermal technique in the uncovered regions. Next, the oxide is anisotropically etched which removes the deposited oxide from horizontal. This is followed by removal of the filler material and, then, the removal of the etching stop layer.
There are deposition processes which can be used to deposit thin films on vertical or inclined surfaces of a substrate relief. However, it is difficult to control the thickness of the layer deposited. Typically, the thickness of the coating decreases as the depth of the relief increases, for example, as the length of the vertical or inclined wall increases. As such, layers deposited using these types of deposition processes have considerable differences in thickness over the length of the relief. These types of deposition processes include plasma-enhanced chemical vapor deposition (PECVD) and diffusion-limited deposition of silicon oxide using tetraethyl orthosilicate (TEOS).
Vertical transistors having a reentrant profile may need monitoring with respect to the amount of overhang or level of reentrant profile. While a deeper reentrant profile assures a clean break between source and drain it can lead to un-gated regions and hence to poorer transistor quality. Therefore, there is a need for a vertical transistor having transistor characteristics with reduced sensitivity to the shape of the overhang or reentrant profile.
There is also an ongoing need to provide semiconductor device architectures that include patterned vertical or inclined device surfaces. There is also an ongoing need to provide manufacturing techniques capable of processing small device features of semiconductor devices without requiring high resolution alignment tolerances. There is also an ongoing need to provide higher current semiconductor devices by improving the series resistance of the device.